1. Field of the Invention
This invention relates to the field of multi-processor data handling systems, each processor having a cache memory. In particular, it relates to apparatus and method for increasing the data handling rate of such systems.
2. The Prior Art
As is known in the art, a large percentage of the commands issued by a processor involve memory commands which necessitate the transfer of data between the processor and a main storage unit. Cache memory units have been positioned between a processor and the main storage unit such that when a fetch command is issued by the processor, rather than fetching only the data at the address requested, a block of data is transferred from the memory storage unit to the cache memory in anticipation that further commands will involve data located at addresses located adjacent to the first requested address. Thus, rather than going to the main storage unit to fetch data with each command, it is only necessary to go to the cache memory unit until the bounds of the data in the cache memory is exceeded. This results in a great savings of time and is particularly valuable in a multiprocessor system.
To ensure that all processors in a multiprocessor system are operating on the same data, and that all data in the cache memory of the processors is identical to the data in the memory storage unit, each time a store command is issued by any processor, not only is the data at that address in the memory storage unit updated, but a check is made of each cache memory to see if the data present in the cache memory at that time needs to be updated. If data to be altered is present, each cache memory where it appears is additionally updated. It can thus be seen, that if each cache memory can correspond to any address in the main storage unit, that a few transactions between one processor and the memory storage unit could tie up the system by checking each cache memory and updating data therein.
U.S. Pat. No. 3,601,812 to Weisbecker discloses a memory system for buffering several computers to a central storage unit and includes an addressing scheme for identifying the memory location of data in the central storage unit such that each computer may retrieve from and restore data to the memory system.
U.S. Pat. No. 4,077,059 to Cordi et al. discloses a hierarchial memory system for a multiprocessing system having two types of memory units on each level. One memory unit is a data store unit and the other is a copyback data store unit which contains all of the changes that have been made either by addition or modification and that are to be copied back to the next lower level of the memory hierarchy. The Cordi et al. memory provides a hierarchial memory system which does not require straight duplication but rather employs copyback and journaling techniques.
U.S. Pat. No. 3,845,474 to Lange et al. discloses a multiprocessor system wherein each processor has a cache store, and the system has a single main memory shared by the processors.